Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations
US4185323A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1978 |
| Grant date | Jan 22, 1980 |
| Priority date | — |
| Expiry date | Jul 20, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem for processing memory requests includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes arrays of memory elements corresponding to a number of storage locations, separate addressing and data output circuits. The system further includes common timing, refresh and control circuits. When the memory request specifies a predetermined type of memory operation, the control circuits generate signals for refreshing a location within the memory unit from which data is not being fetched. The control circuits, upon the completion of the refresh operation, in response to another predetermined memory request, refreshes the corresponding row within the other unit in parallel with fetching data from first unit. Upon completing refresh operations within both units, the control circuits generate a control signal for inhibiting the refresh circuits from performing a mandatory refresh operation, upon a row of memory elements within the memory units in which access to the memory system is inhibited temporarily, enabling memory operations to continue without interruption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.