MOS addressing circuits for display/memory panels
US4189729A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1978 |
| Grant date | Feb 19, 1980 |
| Priority date | — |
| Expiry date | Apr 14, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0228
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A driving and addressing circuit for applying sustaining, writing and erasing voltages to the cells of a multicelled gas discharge display/memory panel. The voltage generating circuitry is isolated from each panel electrode by a pair of oppositely poled diodes individual to that electrode. The diodes provide low impedance paths for the sustainer current and isolate the electrodes from each other. The writing and erasing voltages are coupled to the electrodes through a plurality of complementary MOSFETs, one per electrode, which eliminate all but one of the diode switch circuits per electrode array of the prior art circuitry. The P-channel and N-channel MOSFETs can be formed on separate integrated circuit chips with one of the pair of the diodes while the other diodes are formed on common anode and common cathode integrated circuit chips. In addition, a portion of the addressing circuitry can be formed on the MOSFET chips. Such a circuit configuration substantially reduces the power requirements and circuit complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.