Operand fetch control improvement
US4189768A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1978 |
| Grant date | Feb 19, 1980 |
| Priority date | — |
| Expiry date | Mar 16, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0886
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operand controls are provided in an I-unit using address operand pairs (AOPs), each pair consisting of a request register and a buffer register. When handling variable field length (VFL) instructions with source (SRC) and destination (DST) operand addresses, two AOPs are generally assigned to receive different parts of the first subline (e.g. doubleword) of the SRC operand; this is called a duplicate fetch and is used with any size VFL operand. Efficiency is improved for the special case in which the DST operand has all of its bytes confined to a single subline in main storage by detecting the special case and inhibiting a duplicate fetch signal to the I-unit controls which assign duplicate AOPs to an instruction. The SRC operand may have more than one subline but the alignment controls force all source operand bytes into a single subline for the special case. When the duplicate fetch signal is suppressed, only one AOP is assigned by the controls to the first subline fetch for the SRC operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.