Digital demodulator for phase shift keyed signals
US4190802A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 1978 |
| Grant date | Feb 26, 1980 |
| Priority date | — |
| Expiry date | Aug 17, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital demodulator for differential phase shift keyed (DPSK) signals includes two pairs of 1-bit integrators for continuously taking the phase difference between successive DPSK bits. Each DPSK bit is subdivided into a plurality of bits, for example 15 bits. A weighted output signal having 4 bits is provided by each 1-bit integrator for each of the bits corresponding to a DPSK bit. The weighted output signals from each pair of 1-bit integrators are sine weighted and multiplied. The products are then added together for application to a comparator. The comparator compares the sum of the addition to a predetermined reference signal and provides a demodulated digital signal having a logical state dependent on whether the sum is greater or smaller than the predetermined reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.