Automatic bias adjustment circuit for a successive ranged analog/digital converter
US4193066A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1978 |
| Grant date | Mar 11, 1980 |
| Priority date | — |
| Expiry date | Apr 20, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1014
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An automatic bias adjustment circuit for a successive ranged analog/digital converter (SRADC) that eliminates the need for manual bias adjustments and calibration inputs. The bias correction circuit comprehends dual flip flops that are triggered by selected comparators of the SRADC n bit parallel analog/digital converter. The flip flop output signals control up/down counters whose output bits drive digital/analog converter. The digital/analog converted signals are introduced back into the SRADC analog chain to zero bias errors in a particular sub-range. A disabling circuit prevents operation of the bias adjustment circuits for the first sub-range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.