Tristate logic buffer circuit with enhanced dynamic response
US4194131A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 1978 |
| Grant date | Mar 18, 1980 |
| Priority date | — |
| Expiry date | May 30, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0826
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current mirror transistor is included in a tristate logic buffer circuit, with its base and emitter respectively connected to the base and emitter of the phase splitter transistor and its collector connected to the voltage supply terminal. The emitter size of the current mirror transistor is a multiple of the emitter size of the phase splitter transistor. A high resistance connected between the voltage supply terminal and the collector of the phase splitter transistor provides lower power consumption when the circuit is disabled; and the current mirror transistor supplements the drive current provided by the phase splitter transistor when the circuit is not disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.