Digital hysteresis circuit
US4194186A · kind A · utility
5Cited by
3References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1978 |
| Grant date | Mar 18, 1980 |
| Priority date | — |
| Expiry date | Apr 20, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1014
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Noise induced hunting is eliminated in successive ranged digital/analog converter bias correction circuits by means of a digital hysteresis circuit. The digital hysteresis circuit comprehends a first up/down counter that counts to its extremums from a pre-set intermediate state in response to enable and up/down input signals. For each extremum count an enable output pulse and a reset pulse is generated at the counter output. The enable output pulses are counted by a second up/down counter the output of which drives a digital/analog converter. Each reset pulse resets the first up/down counter to its pre-set state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.