Process for the production of a single transistor memory cell

US4194283A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventor

• Kurt Hoffmann · Taufkirchen, DE

Key dates

• Filing date: Aug 16, 1978
• Grant date: Mar 25, 1980
• Expiry date: Aug 16, 1998

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/901
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In the production of V-MOS single transistor memory cells a simplification of the previous technology is disclosed wherein a process is utilized without epitaxial processes and with a minimum of doping processes. First the source and the drain zone of a field effect transistor forming a memory cell are produced and only then is a V-shaped recess formed at the site of these zones. In one embodiment, one re-doped zone is constructed as a flat zone and is produced on both sides adjacent to a second re-doped zone extending deeper into the silicon crystal. The V-shaped recess is then etched in such a way that the two zones are completely separated by the V-shaped recess. The silicon surface in the V-shaped recess is provided with a thin SiO.sub.2 layer and with a gate electrode covering it. Advantageously the gate electrodes of neighboring V-MOS cells are united into a line. This occurs with one of the two zones of the transistor, whereas the other zone remains separate.