Operation sequencing mechanism
US4197589A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1977 |
| Grant date | Apr 8, 1980 |
| Priority date | — |
| Expiry date | Dec 5, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4494
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism, including a memory, sequences operation in a controlled processor. Each operation is stored in memory together with a portion indicating the current state of predecessor operations required to be completed before execution of the current operation. Also associated with the current operation is provision for at least one address of a successor operation. A predecessor portion is updated as the predecessor operations are performed and at a predetermined state, the current operation is sent to the controlled processor for processing. Following the processing, the operations at the successor addresses have their predecessor portions updated. Thus, the order in which the operations are performed is totally independent of an arbitrary sequencing and instead is dependent only upon availability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.