Shadow masking process for forming source and drain regions for field-effect transistors and like regions
US4198250A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 5, 1979 |
| Grant date | Apr 15, 1980 |
| Priority date | — |
| Expiry date | Feb 5, 1999 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/143
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for substantially reducing the overlap between a gate and the source and drain regions of a field-effect transistor is disclosed. Lateral etching of a polysilicon gate provides overhangs which extend from a gate masking member. Source/drain regions are formed by ion implanting through the gate oxide layer. A small amount of dopant is implanted through the overhangs providing a low concentration of dopant in alignment with the gate. During subsequent processing, this low concentration of dopant does not substantially diffuse as do regions of higher concentration. Significant reduction in Miller capacitance is obtained along with improved punch-through characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.