Column decode circuit for random access memory
US4198700A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1978 |
| Grant date | Apr 15, 1980 |
| Priority date | — |
| Expiry date | Nov 28, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is column decode circuit for a random access memory, which column decode circuit is comprised of a conventional transfer gate transistor, conventional driver transistors and a conventional load transistor. The column decode circuit further includes a chip enable gate transistor according to the present invention. The conventional gate transistor transfers data stored in a corresponding memory cell of the random access memory in accordance with a column address information. The column address information received by the conventional driver transistors connected in parallel causes the above gate transistor to be conductive or nonconductive. Accordingly, the conventional load transistor will apply a voltage of a particular voltage level (Vcc) from a voltage supply to the gate of the transfer gate transistor. The chip enable gate transistor, the load transistor and the parallely connected driver transistors are all connected in series. The thus connected column decode circuit has a very low power consumption and a high speed operating capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.