Method and system for isolating faults in a microprocessor and a machine controlled by the microprocessor
US4200224A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 21, 1978 |
| Grant date | Apr 29, 1980 |
| Priority date | — |
| Expiry date | Aug 21, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/277
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for testing the operability of a microprocessor and a machine controlled by the microprocessor are described. The input/output ports of the microprocessor are tested by propagating, via a test program in the microprocessor, a test logic level along the ports of the microprocessor. As the test logic level propagates, its position is revealed by the successive energization of adjacent light-emissive devices which are external to the microprocessor but connected to the microprocessor ports. Proper propagation of the test logic level is indicated by a corresponding propagation of light across the light-emissive devices. To test the machine, the microprocessor is put in a quiescent but energized state and test logic levels are applied to the ports coupling data between the microprocessor and the machine. Selected functions of the machine are thus exercised independently of the microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.