Processor interrupt system
US4200912A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1978 |
| Grant date | Apr 29, 1980 |
| Priority date | — |
| Expiry date | Jul 31, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital data processor having the capability of handling more than one interrupt wherein one of the interrupts is a fast interrupt is provided. Interrupts are received by a priority network which establishes the priority of the interrupts should more than one interrupt occur at the same time. The output of the priority network is stored in a latch and the output of the latch is coupled to a vector and code logic circuit which encodes the vector address for the interrupt received. Whenever a fast interrupt is received a flag is set in a storage means so that when the system returns from interrupt it will be able to determine whether a fast interrupt had been serviced or not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.