Method of manufacturing a low voltage n-channel MOSFET device
US4205330A · kind A · utility
13Cited by
11References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 17, 1978 |
| Grant date | May 27, 1980 |
| Priority date | — |
| Expiry date | Apr 17, 1998 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/141
Abstract
A novel MOSFET circuit and method of manufacture utilizing a double ion implant process for manufacturing a low voltage high performance n-channel device that includes an enhancement transistor inverter combined with a depletion transistor load. The process starts with high resistivity material and uses a first ion implant process to dope the field region and to give the required threshold voltage for an enhancement device. A second ion implant is used to dope the channel region for the depletion device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.