Multiple length address formation in a microprogrammed data processing system
US4206503A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1978 |
| Grant date | Jun 3, 1980 |
| Priority date | — |
| Expiry date | Jan 10, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/342
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an indexed address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. One of the test conditions indicating whether some of the addressing values used in the generation of the effective address are in a short address format or in a long address format. The address control store word provides signals for controlling the operation of the system, including the branch in between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.