Programmable logic array arrangement
US4207556A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1977 |
| Grant date | Jun 10, 1980 |
| Priority date | — |
| Expiry date | Dec 5, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The programmable logic array arrangement comprises a plurality of cell units formed on a semiconductor substrate and wiring means for interconnecting the cell units. Each cell unit comprises a plurality of electronic elements such as resistors, transistors and diodes which are necessary to form logic circuits, and the wiring means comprises a plurality of bit lines and product term lines which are arranged in the form of a matrix, conductive layers for determining the type and input/output conditions of the logic circuit to be formed. The array arrangement further comprises a group of switching elements connected between the electronic element, bit lines, product term lines, and conductive layers for interconnecting or disconnecting these elements thereby forming desired logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.