Non-volatile ram cell
US4207615A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1978 |
| Grant date | Jun 10, 1980 |
| Priority date | — |
| Expiry date | Nov 17, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A non-volatile MOS memory cell which includes a bistable (flip-flop) circuit with slightly imbalanced loads. An electrically programmable, floating gate device is coupled across a portion of one of the loads to permit selective shunting. When the cell is powered-down (such as at power failure), the floating gate is either charged or discharged as a function of the state of the flip-flop. When power is reapplied, the imbalance caused by the selective shunting forces the flip-flop to its previous state. The relatively small cell does not require resetting, and the stored information is returned in its true (non-complementary) form when the cell is reactivated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.