Programable logic array
US4208728A · kind A · utility
24Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1978 |
| Grant date | Jun 17, 1980 |
| Priority date | — |
| Expiry date | Dec 21, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The decoder portion of a programable logic array (PLA) includes logic devices at crosspoints defined between the word (x) lines and the address (y) lines characteristic of a decoder portion. The devices are operative to combine two or more word lines to activate a single word line in the associated read only memory (ROM) in response to one of two or more possible inputs. The technique is effective even in cases where "don't care" conditions relating the two or more possible inputs cannot be found. A substantial reduction in chip area is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.