Sample and hold circuit
US4209717A · kind A · utility
8Cited by
0References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 7, 1977 |
| Grant date | Jun 24, 1980 |
| Priority date | — |
| Expiry date | Nov 7, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low drift sample and hold circuit is disclosed comprising a transconductance input buffer coupled at its output to a plurality of CMOS inverters through a respective plurality of CMOS switches. The appropriate switches are momentarily addressed by a micro-processor while applying a respective input value to the buffer. The buffer is de-activated prior to the opening of the switch to prevent errors between the sampled and held values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.