Hybrid transistor
US4213141A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 1978 |
| Grant date | Jul 15, 1980 |
| Priority date | — |
| Expiry date | May 12, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device which provides in an input circuit a substantially low reactance and a relatively high resistance within a range of operating frequencies to improve the impedance match between the device and an energy source. The device has a semiconductor die with at least a first and a second bonding terminal having capacitance and resistance between the bonding terminals. At least a first bond lead electrically connects the first bonding terminal to a first metallic contact area. Means connects at least a second bond lead between the second bonding terminal and a second metallic contact area. At least a third bond lead electrically connects the first bonding terminal to the second metallic contact area to form an inductance to interact with the capacitance of the semiconductor die within the operating range of frequencies thereby to increase the input impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.