Junction field effect transistor
US4215356A · kind A · utility
6Cited by
1References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 19, 1978 |
| Grant date | Jul 29, 1980 |
| Priority date | — |
| Expiry date | Apr 19, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/357
Abstract
An N.sup.- semiconductor layer is epitaxially grown on an N.sup.+ semiconductor substrate serving as a drain region and overlaid with an N type epitaxial layer. Two opposite P.sup.+ gate regions are disposed in the surface portion of the N layer to define a channel region between them, and an N.sup.+ source region is located above the channel region. That portion of the N layer located between each gate region and the N.sup.- layer has a thickness not smaller than one-half of the channel width of the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.