Interface adaptor architecture
US4218740A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1977 |
| Grant date | Aug 19, 1980 |
| Priority date | — |
| Expiry date | Jan 5, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of system data bus buffer circuits coupled to a system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. The direction of data flow in the peripheral data bus is controlled by a data direction register. Data from the system data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register and the control register are transferred via an output bus to the system data bus buffers. Control signals are generated by select, read/write control, and register select logic which provides signals on a control bus coupled to the input register, the data register, the control register, and the data direction register to control data transfers between the various buses, registers, and buffer circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.