Combined timekeeper and calculator with low power consumption features
US4218876A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1977 |
| Grant date | Aug 26, 1980 |
| Priority date | — |
| Expiry date | Nov 23, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3228
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A combined timekeeper and calculator implemented on an LSI semiconductor chip includes a generator stage for generating basic clock signals and system clock signals which are obtainable by modifying the basic clock signals, and a processor stage responsive to the supply of the system clock signals for performing the operations required for the timekeeper mode and calculator mode. The basic clock signals also are modified to create second signals useful in the timekeeper mode. The generator to supply the processor unit with the system clock signals while the second signal is being generated. Upon completing the operations by the processor unit, a clock control circuit prevents the processor unit from being supplied with the system clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.