Cache memory control system
US4219883A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1979 |
| Grant date | Aug 26, 1980 |
| Priority date | — |
| Expiry date | Mar 22, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Block information from a main memory, which is registered in an address register, is applied to a directory. A bank address in the main memory is taken out from the respective locations defined by the block information in each bank of the directory. A comparator compares the bank address with a bank address of the main memory registered in said address register. The output signal from the comparator is applied as a control signal to a control ROM. The directory memory applies an address signal to the control ROM. Upon the application of the address signal, the control ROM produces the contents (control information) of the location defined by the address signal and the contents is loaded into the directory memory. The control information determines the earliest used bank in the cache memory and determines the bank to which the contents of the main memory is loaded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.