Phase locked loop for deriving clock signal from aperiodic data signal
US4222013A · kind A · utility
Inventors
Key dates
| Filing date | Nov 24, 1978 |
| Grant date | Sep 9, 1980 |
| Priority date | — |
| Expiry date | Nov 24, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit (100) for generating a periodic clock signal from a controlled oscillator circuit (130) in phase coincidence with a synchronous aperiodic data input signal is disclosed. A pulse of the data signal and a corresponding pulse of the clock signal are applied to a bistable circuit (FF1) having an output signal indicating which of the pulses occurs first in time. The pulses are further applied through delay circuitry (DLY1, DLY2) to another bistable circuit (FF2) having an output signal indicative of the magnitude of phase difference between the pulses. The output signals of the bistable circuits (FF1, FF2) are applied to a multilevel driver circuit (140) which generates an error correction signal pulse defining magnitude and direction of a correction signal to be applied to the oscillator circuit (130).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.