Digital logic for separating data and clock in Manchester-encoded data
US4222116A · kind A · utility
12Cited by
11References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 5, 1978 |
| Grant date | Sep 9, 1980 |
| Priority date | — |
| Expiry date | Sep 5, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4904
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic includes a shift register (RBA-RBH, FIG. 8J) to separate the data and clock signals in a Manchester-encoded data stream. The Manchester encoding is adaptable to any data rate simply by changing the frequency of a high speed clock associated with the shift register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.