Display stabilization circuit
US4224569A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 1978 |
| Grant date | Sep 23, 1980 |
| Priority date | — |
| Expiry date | Jul 19, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R15/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A stabilized display for electronic instruments that make voltage measurements, frequency measurements, and the like is disclosed. This stabilized display includes a counter, a register, a comparator, and control logic. The counter generates counts, during spaced apart time intervals, that are representative of measurements made by the instrument. Selected ones of these counts are transferred to the register in response to a LATCH signal, where they are displayed. The comparator connects to the counter and the register. It generates output signals indicating whether or not the contents of the counter and register are equal. These output signals are received by the control logic, which generates the LATCH signal in response to a predetermined sequence of non-equality indications from the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.