Multibus processor for increasing execution speed using a pipeline effect
US4228498A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 1977 |
| Grant date | Oct 14, 1980 |
| Priority date | — |
| Expiry date | Oct 12, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3854
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing apparatus having at least three buses and a plurality of elementary function modules in circuit connection therewith, provides increased execution speed by implementing a pipeline effect. Each module is connected to at least one of the buses and at least one of the modules is connected to at least three of the buses. The buses each comprise a plurality of individual lines organized into groups: a group of source address lines, a group of destination address lines, and a group of data carrying lines. A control element is connected to each of the buses for directing the operation of the apparatus and the control element places source and destination addresses on the bus source address and destination address lines respectively for effectively connecting or configuring the function modules according to a selected program controlled configuration. The apparatus is useful in carrying out a plurality of machine operations during a single machine instruction cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.