Electrically reprogrammable non volatile memory
US4228527A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1979 |
| Grant date | Oct 14, 1980 |
| Priority date | — |
| Expiry date | Feb 22, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically reprogrammable non-volatile memory device is disclosed which includes complementary MOS transistors provided with a polycrystalline silicon floating gate electrode in a common n.sup.- -type substrate. The device comprises three main parts. The first part, which is used for writing, comprises a p-channel writing transistor, a p-channel control transistor and a resistance element. The second part, which comprises a second gate electrode capacitance coupled with the floating gate, is used for erasing. The third part is used for performing information read-out and consists of a p-channel transistor the gate of which forms a portion of the floating gate and the drain of which is connected to a read-out terminal and to the terminal of a loading element having its other terminal connected to a negative supply potential. This device enables writing control to be performed using a logical signal of the order of one volt, read-out being also performed with a low voltage value, with low energy consumption. Erasure of information can be performed electrically and the retention time is of several years.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.