Distributed arbitration circuitry for data processing system
US4229791A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1978 |
| Grant date | Oct 21, 1980 |
| Priority date | — |
| Expiry date | Oct 25, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses on a priority basis. A central clocking circuit generates timing signals that control such communications by defining bus cycles on a synchronous basis and each nexus contains priority circuitry that operates in response to these signals. Each nexus that requires access to the interconnection asserts a transfer request signal at a predetermined time during each bus cycle. Priority arbitration circuitry in each nexus receives all such requests and samples them at another, later, time during each bus cycle. When a nexus is transmitting a request and no nexus with a higher priority is transmitting a request, that nexus takes control of the interconnection. A transfer during a subsequent bus cycle to another nexus can be prevented during certain types of transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.