Digital clock phase recovery circuits for data receiver
US4229823A · kind A · utility
6Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1979 |
| Grant date | Oct 21, 1980 |
| Priority date | — |
| Expiry date | Jun 11, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
To stabilize the phase of bit rate clock signals recovered from a self-clocking data signal, e.g., a Manchester coded signal, extra signal level transition pulses (58) occurring during intervals of successive bits of the same info bit type are inverted (59) to reinforce the desired phase of the bit-rate frequency component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.