Circuit and method for paralleling power transistors
US4234805A · kind A · utility
15Cited by
3References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 15, 1978 |
| Grant date | Nov 18, 1980 |
| Priority date | — |
| Expiry date | Mar 15, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method of paralleling power transistors connected as a Darlington circuit or device for use with electric motor controls. The circuit is comprised of a plurality of Darlington devices having a drive circuit from a motor controller connected to a common base connection and a plurality of active pull-down circuits for reducing the rise and fall times and effectively controlling the storage times of the power transistors. The active pull-down circuits are capacity coupled to an inverted drive signal to synchronize the turn-off time and speed-up discharge of storage in the power transistor circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.