Programmable frequency divider and method
US4234849A · kind A · utility
10Cited by
7References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 10, 1977 |
| Grant date | Nov 18, 1980 |
| Priority date | — |
| Expiry date | Nov 10, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high frequency programmable frequency divider operates in a digital manner to divide the frequency of an applied signal by an integer value greater than five. The frequency divider combines emitter coupled logic (ECL) devices to perform a frequency divide algorithm at frequencies of 220 MHz.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.