Time-shared, multi-phase memory system with error checking and data correcting
US4234918A · kind A · utility
6Cited by
9References
8Claims
0Family size
Assignee
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Key dates
| Filing date | May 31, 1977 |
| Grant date | Nov 18, 1980 |
| Priority date | — |
| Expiry date | May 31, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-phase, bit addressable, variable field memory system partitioned into a plurality of individually addressable memory stacks and employing time-shared accessing circuitry as well as time shared error detection and data correction means, whereby serial memory stack accessing along with serial error checking and correction are achieved without significantly increasing the overall memory accessing time over that obtained for parallel accessing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.