Instruction set modifier register
US4236204A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1978 |
| Grant date | Nov 25, 1980 |
| Priority date | — |
| Expiry date | Mar 13, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30196
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction set modifier register, comprising one or more bistable latches which are loadable under program control, is provided for use in a processor in conjunction with an instruction register. An instruction decoding circuit and an instruction execution control logic circuit, responsive to both the instruction register and the instruction set modifier register, generate a first set of control signal combinations corresponding to a first instruction set when the instruction set modifier register is in a first state and generate a second set of control signal combinations corresponding to a second instruction set when the instruction set modifier register is in a second state. The processor is thus able to execute more than one set of instructions, utilizing the same instruction decoding circuitry and instruction execution control logic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.