Access-time reduction control circuit and process for digital storage devices
US4236205A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1978 |
| Grant date | Nov 25, 1980 |
| Priority date | — |
| Expiry date | Oct 23, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/383
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and process for controlling access to a digital storage device is disclosed. The process involves reading a control word from a control store and partially decoding an address field of the control word to predict the storage location to be accessed. The address field is subsequently fully decoded to determine the actual storage location to be accessed. Prior to completion of this decoding step, an access to the predicted location in main storage is initiated. In the event the actual storage location to be accessed differs from the predicted one, the memory access previously initiated is overridden and an access to the actual storage location is initiated. A digital compouter system incorporating a circuit for carrying out this process exhibited significantly reduced running times for typical computer programs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.