Central processor unit for executing instructions of variable length
US4236206A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1978 |
| Grant date | Nov 25, 1980 |
| Priority date | — |
| Expiry date | Oct 25, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4484
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.