High speed latching comparator
US4237387A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1978 |
| Grant date | Dec 2, 1980 |
| Priority date | — |
| Expiry date | Feb 21, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A window comparator latch network is disclosed for track or sampling a differential input signal and for "latching" the input signal upon a clock signal. Several latch networks are disclosed for both single and dual differential input configurations. The dual input configuration includes first and second pairs of differential transistors which are coupled to a differential regenerative and latching pair of transistors. The regenerative and latching transistor pair provides an output signal having first or second states only upon the required clock signal being applied to a current switching transistor pair. Negative differential signals applied to both first and second pairs of differential transistors results in a "0" logic state output signal from the regenerative and latching transistors. A positive differential signal results in a logic "1" output state. Positive input signals applied to both differential transistors results in a logic "0" output state. Thus the latch network provides a "window" output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.