Gated baseline corrector
US4237424A · kind A · utility
9Cited by
6References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1978 |
| Grant date | Dec 2, 1980 |
| Priority date | — |
| Expiry date | Aug 18, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Input pulses are coupled through a delay network to a pulse amplifier. The amplifier includes feedback circuitry for correcting its output to a particular baseline level, generally zero volts. Within the amplifier feedback path is a gate, which is normally closed. Input pulses are also coupled to a pulse detector; whenever an input pulse is detected, the baseline gate in the amplifier feedback path is open, and the dynamic feedback operation is temporarily inhibited. During this time, the most recent previous level of baseline correction is retained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.