Patent · US Expired

Dynamic semiconductor memory read/write access circuit

US4238841A · kind A · utility

18Cited by

4References

5Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Rainer Clemen · Böblingen, DE
Joerg Gschwendtner · Eßlingen, DE
Werner Haug · Thalwil, CH

Key dates

Filing date	Dec 14, 1979
Grant date	Dec 9, 1980
Priority date	—
Expiry date	Dec 14, 1999

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/404
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

To the known sense latch already existing in a bit line pair in an FET memory, and to the two bit switches in each bit line another latch is arranged in series which furthermore is coupled to the common data input and output via a write driver on the one side and a read driver on the other. Both latches are of an identical structure and controlled by the same pulses in the read as well as in the write phase. The data path via the write driver and the read driver up to, or from, the additional latch is respectively designed as unidirectional double rail line, and selectively connectable via the bit switches with the bidirectional double rail line to the respective bit line pair.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.