Parallel interconnect for planar arrays
US4239312A · kind A · utility
44Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1978 |
| Grant date | Dec 16, 1980 |
| Priority date | — |
| Expiry date | Nov 29, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A large scale parallel architecture in which many parallel channels numbering 10.sup.2 or more operate simultaneously to create a natural and efficient organization for processing two-dimensional arrays of data. The architecture comprises a plurality of stacked integrated circuit wafers having top and bottom surfaces, electric signal paths extending through each of the wafers between the surfaces, and micro-interconnects (smaller than 50 mil) on the surfaces of adjacent wafers interconnecting the respective electric signal paths with a topographical one-to-one correspondence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.