Fault-tolerant clock system
US4239982A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1978 |
| Grant date | Dec 16, 1980 |
| Priority date | — |
| Expiry date | Jun 14, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault-tolerant clock system for providng digital timing signals (system clock signals) is provided by a plurality of clock sources. Each clock source receives as inputs the generated clock signals from all the other clock sources and contains receiver circuitry to derive a system clock signal from said clock sources which is the consensus clock signals of the other sources. Each clock source generates and distributes to the other clock sources a clock signal which is phase locked to the derived system clock from its clock receiver. In a system of (2r+2) clock sources (r+2) of them will remain phase locked to each other despite up to r clock source failures. Any clock receiver responsive to any (2r+1) of the clock sources can therefore derive a correct system clock despite up to r clock source failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.