Semiconductor devices
US4241424A · kind A · utility
7Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1978 |
| Grant date | Dec 23, 1980 |
| Priority date | — |
| Expiry date | Sep 27, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel mode of operation of an array of MNOS memory transistors is provided which employs the punch through mode of erase and enables a single transistor memory cell to be used. It being arranged that all `bits` are written into the `1` state and bits are selectively erased to provide the required data pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.