MOS Input circuit with selectable stabilized trip voltage
US4242604A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 1978 |
| Grant date | Dec 30, 1980 |
| Priority date | — |
| Expiry date | Aug 10, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is an integrated buffer circuit having a selectable stabilized trip voltage. The circuit includes an input stage and a reference stage. Each of these stages includes an MOS field effect transistor, a substantially constant resistance device coupling the drain of the input transistor to a bias source, and a device having a resistance that is variable in response to control signals coupling the source of the input transistor to another bias source. The reference stage is biased in the linear region at the selectable trip voltage. A signal generated at the drain of the transistor in the reference stage is connected to all of the variable resistance devices as the control signal. This signal varies the variable resistance in such a way as to compensate for threshold voltage variations in the transistor of the input stage and thus stabilize the selected trip voltage of the input stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.