Dielectrically isolated high voltage semiconductor devices
US4242697A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1979 |
| Grant date | Dec 30, 1980 |
| Priority date | — |
| Expiry date | Mar 14, 1999 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/914
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure for achieving closely spaced high voltage devices in integrated circuits. The devices are formed in single crystalline tubs (11) in a polycrystalline substrate (10). In order to prevent the potential of the substrate from causing breakdown of the devices, there is included between the single crystalline tubs and the polycrystalline substrate a semi-insulating layer (13) which has trapping states capable of taking on charge from the single crystalline region. The shielding provided by the semi-insulating layer permits the surface regions of the device to be made closer to the polycrystalline substrate and the tubs to be made more shallow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.