Tuner with phase locked loop synthesizer
US4244055A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1978 |
| Grant date | Jan 6, 1981 |
| Priority date | — |
| Expiry date | Oct 16, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J5/0272
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL tuning device in a receiver uses a digital memory board and array of photo-transistors scanning the memory board for station selection. When the transistors are lined up with a column, a digital output is fed to a switching device and to a programmable frequency divider. Muting action is released when the output is delivered to the divider, but, when the array is between columns, muting action takes place. In one embodiment, the photo-transistor output is fed to a latch and to an OR gate serving as the switch. A one-shot is triggered in response to the setting of the OR gate at an H level. Digital information is fed to the programmable frequency divider from the latch until the one-shot is fired. In another embodiment, the latch and one-shot are eliminated. Photo-transistor output is fed to both an OR gate and the frequency divider. The OR gate controls a switch that closes muting switches only when information is being generated by the photo-transistors. However, when the sensor array is between signals the tuner is maintained in a muted state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.