Controller for data processing system
US4245307A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1979 |
| Grant date | Jan 13, 1981 |
| Priority date | — |
| Expiry date | Sep 14, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4213
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller for at least one secondary storage device for use in a data processing system having a system bus which accommodates a device or a CPU that first acquires control, a device bus that has the same address, data and control format as the system bus and a cache bus which maintains its own timing for address and data signals. The controller has means for transferring the control signals between the device bus and the system bus to establish control over the system bus by the secondary storage device. The data, address and control signals are transferred between the device bus and the cache bus in accordance with the cache bus timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.