Processing system with dual buses
US4245344A · kind A · utility
183Cited by
5References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 2, 1979 |
| Grant date | Jan 13, 1981 |
| Priority date | — |
| Expiry date | Apr 2, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system is disclosed in which transfers between processors and memory are made on dual redundant buses. In a transfer, the transmitting unit sends the same information simultaneously on each of the buses. The receiving unit makes parity checks on each bus, and compares the information received on one bus with that received on the other bus. The receiving unit includes means for implementing a decision rule, based on these checks and comparison, to choose from which bus to take information, if either.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.