Digital recognition circuits
US4246569A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1979 |
| Grant date | Jan 20, 1981 |
| Priority date | — |
| Expiry date | Aug 20, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/56
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit for monitoring digital data comprises a shift register for receiving the data to be monitored, the outputs of the shift register being fed either directly to the inputs of memory devices or via controllable gates. The memories are programmed to detect the number of logical `ones` present in the shift register, and the detected number is compared with a reference to determine whether the data should be accepted or rejected. In one mode of operation, the controllable gates alter the inputs to the memories such that they are all the same when the correct data is in the shift register. In another mode of operation, the gates supply the memories with unaltered data and the circuit can detect errors because the data is coded in such a manner that each block of data should contain the same number of digits and the same number of logical `ones`.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.