Punch-through load devices in high density static memory cell
US4247915A · kind A · utility
31Cited by
1References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 2, 1979 |
| Grant date | Jan 27, 1981 |
| Priority date | — |
| Expiry date | Jan 2, 1999 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory of the static type employs a pair of cross-coupled driver transistors and a pair of access transistors along with load devices which are punch-through elements resembling short channel MOS transistors without gates. The punch-through elements each have an electrode integral with the drain of one of the driver transistors, and another electrode coupled to a voltage supply. A cell layout of very small size is possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.